By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The attention of sign sampling and quantization at excessive pattern charges with low strength dissipation is a crucial objective in lots of purposes, includ ing moveable video units akin to camcorders, own verbal exchange units comparable to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic information detection, etc. This paper describes structure and circuit techniques for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive velocity is taken to suggest sampling premiums above 1 Mhz. within the first part the dif ferent conversion suggestions acceptable during this variety of pattern charges is dis stubborn. Following that the actual difficulties linked to energy minimization in video-rate pipeline ADCs is mentioned. those comprise optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal strength dissipation. for example of the appliance of those tech niques, the layout of a power-optimized lO-bit pipeline reduction converter (ADC) that achieves =1. sixty seven mW consistent with MS/s of sampling expense from 1 MS/s to twenty MS/s is defined. 2. strategies for CMOS Video-Rate relief Conversion Analog-to-digital conversion strategies may be labeled in lots of methods. One handy technique of evaluating concepts is to envision the variety of "analog clock cycles" required to supply one powerful output pattern of the sign being quantized.
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Additional info for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
In BiCMOS technology, the gain can be improved by combining the high current gain of a MOS transistor and the large transconductance of a bipolar transistor. 47 References [I] G. D. Thesis, Delft University of Technology, Delft, The Netherlands, 1992. H. I. d. S. Appl. No. 4,555,673, Nov. 26,1985. H. Huijsing and D. Linebarger, "Low-Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges", IEEE I. 6, Dec. 1985, pp. 1144-1150.  I. M. I. H. Huijsing, "l-V Operational Amplifier with Rail-to-Rail input and output Ranges"  R.
I I Rl C1 VEE Fig. 30. Three-stage amplifier with multipath nested Miller compensation. Multipath Nested Miller compensation structure. as is shown in Fig. 15]. The circuit consists of a three stage Nested Miller opamp and an additional input stage. Q33"Q34' This input stage bypasses the intermediate stage. Q21-Q22' The result is an amplifier which has a three-stage gain path and a two-stage high-frequency path. 31 shows the frequency characteristic of the Multipath Nested Miller compensation. The gain and the high frequency path can be easily matched by making the unity-gain frequencies of both paths equal.
Bandwidth versus Power Supply The bandwidth of a one stage amplifier is given by: B=~ (18) 21tCL For a bipolar stage (18) can be written as: B = Ie (19) :---;-;-~ 21tUT C L If (19) is divided by the supply-power the following expression is obtained B 1 1 (20) It is obvious that the lower the supply voltage the higher the bandwidth-tosupply-power ratio. 1 is the mobility of the charge carriers, Cox is the normalized oxide 37 capacitance. W is the width of a transistor. L is the length of a transistor and VTH is the threshold voltage.